The present invention disclosed herein relates to semiconductor memory apparatuses, and more particularly, to a data output circuit and method for strengthening the drivability of a semiconductor memory apparatus when the last output data transitions in voltage level.
Data input/output operations of a synchronous dynamic RAM (SDRAM) are usually carried out in sync with rising edges of a clock signal. Meanwhile, in a double data rate SDRAM (DDR SDRAM), input/output operations are conducted in sync with falling edges as well as rising edges of a clock signal, hence the speed of data input/output operations are double that of a typical SDRAM. Thus, a high-frequency semiconductor memory apparatus like DDR SDRAM is configured to generate a clock (hereinafter, rising clock) enabled at a rising edge of a clock signal output from a delay locked loop (DLL) circuit during a data output operation, and a clock (hereinafter, falling clock) enabled at a falling edge of the clock signal of the DLL circuit. Then, after storing data (hereinafter, rising data) output when the rising clock is activated and data (hereinafter, falling data) output when the falling clock is activated to a pipe register, the data is output from the pipe register in sequence to accomplish a high-frequency data output operation.
A conventional data output circuit will be described with reference to FIGS. 1 and 2 as follows.
FIG. 1 is a block diagram showing a structure of a conventional data output circuit in a conventional semiconductor memory apparatus, which outputs four bits of data.
The data output circuit shown in FIG. 1 is comprised of a pipe register 10 storing four bits of data DATA<0:3> at a time and alternately outputting rising and falling data RDATA and FDATA in response to four pipe output control signals POUT<0:3>; a pre-driver 20 generating pull-up and pull-down signals PLLUP and PLLDN from driving the rising data RDATA in active periods of a rising clock RCLK and the falling data FDATA in active periods of a falling clock FCLK in accordance with the state of an output enable signal OE; and a main driver 30 generating a last output data ODATA in response to inputs of the pull-up and pull-down signals PLLUP and PLLUP.
The pipe register 10 stores the four input data bits DATA<0:3> at the same time. After storing the data, when the pipe output control signal POUT<0> is activated, the rising data bit RDATA<0> is output from the pipe register 10. When the pipe output control signal POUT<1> is activated, the falling data bit FDATA<0> is output from the pipe register 10. When the pipe output control signal POUT<2> is activated, the rising data bit RDATA<1> is output from the pipe register 10. When the pipe output control signal POUT<3> is activated, the falling data bit FDATA<1> is output from the pipe register 10.
The pre-driver 20 drives the rising and falling data RDATA and FDATA only in an active period of the output enable signal OE. When the output enable signal OE is inactivated, the pull-up and pull-down signals PLLUP and PLLDN output from the pre-driver 20 are each fixed to high and low levels respectively, without being influenced by the rising and falling data RDATA and FDATA. But, when the output enable signal OE is activated, the pre-driver 20 drives the rising and falling data RDATA and FDATA at active periods of the rising and falling clocks RCLK and FCLK, respectively. When this occurs, the pipe output control signals POUT<0> and POUT<2> are generated from the rising clock RCLK, while the pipe output control signals POUT<1> and POUT<3> are generated from the falling clock FCLK. Thus, when the rising and falling clocks RCLK and FCLK are activated, the rising data bits RDATA<0>, RDATA<1>, RDATA<2>, and RDATA<3> are driven in sequence. When this occurs, the pull-up and pull-down signals PLLUP and PLLDN output from the pre-driver 20 are at the same logical value.
The voltage level of the last output data ODATA generated from the main driver 30 is determined by the voltage levels of the pull-up and pull-down signals PLLUP and PLLDN. But, if a high level pull-up signal PLLUP and a low level pull-down signal PLLDN are applied to the main driver 30 when the output enable signal OE is inactive, the voltage level of the last output data ODATA is in a floating state and thus regarded as being invalid for data.
FIG. 2 is a timing diagram illustrating an operation of the data output circuit shown in FIG. 1.
From FIG. 2, it can be seen that the pipe output control signals POUT<0:3> are sequentially activated in response to the rising and falling clocks RCLK and FCLK which are generated from a DLL clock DLL_CLK. Responding to the sequential activation of the pipe output control signals POUT<0:3>, the four bits of the input data DATA<0:3> are generated as the rising data bit RDATA<0>, the falling data bit FDATA<0>, the rising data bit RDATA<1>, and the falling data bit FDATA<1>, respectively. Then, if the output enable signal OE is activated, the pull-up and pull-down signals, PLLUP and PLLDN, are generated with predetermined levels from the rising data bit RDATA<0>, the falling data bit FDATA<0>, the rising data bit RDATA<1>, and the falling data bit FDATA<1>. The pull-up and pull-down signals PLLUP and PLLDN define the logical value of the last output data ODATA.
However, in the data output circuit operating in the aforementioned mode, time is required for varying the value of the last output data ODATA, i.e., transitioning the voltage level of the last output data ODATA. The time requirement is caused by an internal impedance of the data output circuit. When the data output circuit is operating at high frequency, it is also necessary to transition the level of the last output data ODATA at high frequency. However, since the impedance is constant, it is difficult for the last output data ODATA to reach its correct target level.